>Building Application-specific Integrated Circuit (ASIC) for zero-knowledge proof (ZKP), aiming at 100x faster proving speed. Will support mainstream ZKP schemes and curves. Also aiming at at least 2x cheaper than GPU-based system with higher energy efficiency
>Will also have a complete Field Programmable Gate Arrays(FPGA) prototype during ideation process, therefore if the ASIC tapeout fails, they still have a complete product to compete in market
>In the future, might expand into their own L2 endeavor, but that’s still a stretch from now
Shibo Chen陈士博, RTL (Register Transfer Level) Engineer
>UMichi 大学本科毕业，现 UMichi 博士最后一年。研究方向是计算机体系架构
>博士期间先后在 Tenstorrent 实习
>现全职参与 RTL 的开发
Sihao Liu刘思皓, RTL Engineer
>UCLA 博士最后一年。研究方向是计算机体系架构， 论文多次获得 IEEE Micro Top Picks 荣誉
>现全职参与 RTL 的开发
Bangyan Wang, RTL Engineer
>清华大学电子系本科毕业, 目前 UCSB 博士最后一年, 研究方向是计算机体系架构。
>博士期间先后在阿里巴巴、亚马逊实习
>现全职参与 RTL 的开发
Advisor team please refer to Cysic团队.pdf
Pros
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>Market Prospection: ZKP hardware acceleration is an emerging market. Most direct/indirect competitors (Ingonyama is working on cloud ZKP, Supranational working on library, consulting, Proof-aas) are born in the past 6 months. If Zero-knowledge emerge to be the winner of the L2 space (which I personally believe), then hardware acceleration is a crucial backbone for a vibrant ecosystem
>Accleration with Algorithm vs Hardware: unlike the traditional AI/ML space, ZKP isn’t yet optimized algorithmically. Notably, the field is currently stuck with a dilemma on asymptotic improvement, where the following four are all true (quoting Sebastien La Duca, working on ZK infra and contribute to Ponky2 and Starky): 1) doesn't come with large constant factors, 2) doesn't have bad concrete performance (i.e. efficient in theory, but extremely unfriendly to modern computer architecture), 3) isn't only applicable in certain circumstances, 4) doesn't come with tradeoffs. We are still not sure when breakthrough in research will occur. Hardware can, in contrast, render practical improvement now
>Expertise: All-star team with great track record in cryptography and hardware. Based on information gathered, the Cysic team excels both qualitatively and quantitatively. Advisory team is also all-star, with the notable 陈溪教授 (NYU Stern终身教授。卡内基梅隆大学计算机学院博士。研究方向主要是机器学习和在电子商务领域中的应用)
Cons
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>At the time of writing, we are yet to receive a clear answer from Leo Fan the CEO on running Cysic full time. Given his recent AP promotion and prospective career in academia (which means grinding period for tenure in the near future), if Leo takes on two together, he might put less energy into Cysic. We are in contact with him on this topic
>At the time of writing, Leo’s equity is equal to his CTO, Bowen Huang, and since the team is all Chinese, this could be a potential attention point. We are also in conversation with Leo on this topic
>ASIC, in contrast to FPGA, which is a more general-purposed instrument that can adapt to tasks from various entity, is very specific (think about ASIC as optimizing toward a specific circuit). This means investing into ASIC is pseudo-equivalent to believing a singular/oligarchical future of the ZK space. Since the L2 ZK space is yet to have a winner (with Starkware and Polygon being the two leading in public coverage), this could be some risk in hindsight.
Competitive Landscape
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The hardware acceleration space is relatively nascent. No clear winner has claimed the throne yet, with only a few direct/indirect competitors listed below.
>DZK, working on FPGA, invested by Chainlink and Filecoin. Comparatively speaking, the two founders of DZK are also PhD in this space and are competitive qualitatively
>Supernational, working on FPGA/GPU and provides consulting service, not yet raised, in collaboration with Delendum (Ventali Tan)
>Snarkify, working on FPGA, founded by Jiannan Ouyang
>Ingonyama (indirect competitors, potential collaborator) is working on cloud ZKP and algorithmic optimization
Overall this space is highly prowess-driven and betting on a technically strong team seems to be the winning hand. A bit of ASIC vs FPGA vs GPU is listed below and in the deck
>Programmability: ASIC will be equipped with zkp-specific ISA (Instruction Set Architecture, part of the computer structure that defines how the CPU is controlled by the software)
>IO Bandwidth: ASIC → PCIE gen 4 x32/x16 or higher, GPU → PCIE gen 4 x16, FPGA → PCIE gen4 x8
>Cost: GPU ~$1200, FPGA ~$1500, ASIC will stand out if number of chips >5k (beyound 5k, they can break even. At 10k chips, they can sell at $750 and still make ~50% gross profit)
Term
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Deck says $4M, Leo later said they only really need $2M and don’t want to dilute too much equity. Cysic is oversubscribed and term sheets have been offered, but the final list of investor is yet to be finalized
Cysic Deck.pdf
3.6 MB
Cysic团队.pdf
168.1 kB
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Cysic - Memo